A chip select function has long been used in memories to disable a memory circuit to reduce power consumption. The memory is not responsive to external address signals when deselected by the chip select signal. Although there is power savings, there is also the potential problem of a loss of speed when switching from the deselected mode to the selected mode because the circuitry is powered down and there is a recovery time. One of the major power losses in CMOS is the first input stage for an input signal because it generally must be compatible with TTL signal levels. A logic high TTL signal may be as low as 2.0 volts. Such a logic high, which is suppose to turn off a P channel transistor, will cause the input P channel transistor to be conductive and thus waste power. Consequently, it is desirable to disable the input stage of as many input signals as is feasible during deselect mode. In many modern memories, however, address transition is used for equillibrating bit lines as well as for other functions, for the purpose of increasing the speed of operation which is reflected in lower access times. When an address buffer which receives an external address signal receives a logic low input, the transition from the deselect to select modes will cause the buffer to provide an address transition which is detected as such if the buffer is disabled during the deselect mode. There is then an unnecessary equalization pulse generated as a consequence of the address buffer being disabled during the deselect mode. There is, however, a delay in generating the equalization pulse because there is a delay in enabling the address buffer because there is an unavoidable delay in responding to the chip select signal. This causes a longer access time for the case in which the memory circuit is coming out of the chip select mode than for the case of a address transition during the select mode. The alternative to having the extended access time has been to not disable the address buffers during the deselect mode and incur the additional power loss.